Generally speaking, such an integrated test device designed to test a structure, for example a chain of flip-flops, comprises a test pattern generator configured for generating a series of known data, and a signal analyzer configured for comparing the series of known data and a test signal coming from the propagation of the series of data within the structure to be tested, and for delivering, for example, a bit error rate depending on the result of the comparison.
However, the length of the series of known data delivered by the generator is generally closely linked to the number of flip-flops in the structure to be tested.
In this respect, reference may be made to the document “Autonomous bit error rate testing at multi-gbits/s rates implemented in a 5 AM SiGe circuit for radiation effects self test (CREST)”, P. Marshall, M. Carts, S. Currie, et al, IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2446-2454, December 2005 (incorporated by reference) which describes a test device comprising a test pattern generator whose length of the pattern is 2^7-1, or 127 bits. This test device is consequently only compatible with a structure to be tested, for example a shift register, comprising 127 flip-flops.
In other words, such a conventional test device is not interchangeable for testing structures having different numbers of flip-flops.